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High Mobility Materials for CMOS Applications provides a comprehensive overview of recent developments in the field of (Si)Ge and III-V materials and their integration on Si. The book covers material growth and integration on Si, going all the way from device to circuit design. While the book's focus is on digital applications, a number of chapters also address the use of III-V for RF and analog applications, and in optoelectronics. With CMOS technology moving to the 10nm node and beyond, however, severe concerns with power dissipation and performance are arising, hence the need for this timely work on the advantages and challenges of the technology.

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Academic collection --- 621.382.3 --- #BIBC:T2000 --- Transistors --- Theses --- 621.382.3 Transistors

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In order to continue increasing the circuit functionality per area, a novel concept has been envisioned which consists of stacking transistors on top of each other sequentially in the same front-end process flow ("3D Sequential Integration"). This approach would enhance device density per chip area, without requiring further reduction of the device dimensions. Additional potential advantages include a simplified co-integration of heterogeneous devices technologies (e.g., Si and Ge/III-V channel FETs; logic and optical devices) and a reduction of the length of interconnection lines, with the associated beneficial reduction of signal propagation delays. The PhD research will focus on overcoming the gate stack challenges associated with the thermal budget constraints of a 3D Sequential Integration. These challenges are two-fold: on one hand, a sufficiently reliable high-k dielectric stack needs to be developed for the top layer without resorting to high temperature steps for defect curing. On the other hand, due to the limitations on the process temperature, doping activation and contact formation in the top transistor might need to be achieved with longer thermal steps, which might in turn affect the reliability of the bottom transistor (e.g., inducing undesirable diffusion of dopant atoms and other species present in the gate stack). As a consequence, the fabrication of the bottom devices might also need to be revised. The daily work will involve electrical and physical characterization of fabricated test structures (MOS capacitors and transistors); interpretation of the experimental trends based on modeling and simulations; definition of experiments and feedback to device integration engineers, in iterative learning cycles.

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The key to continuous improvement in MOSFET performance is scaling. However, device down-scaling poses some fundamental limitations. One of the common challenges of transistor scaling is the short-channel effect, where a gate-all-around architecture (GAA) could help. In addition, it is getting difficult with lateral devices to extend the technology roadmap beyond sub-10nm technology nodes while respecting the rules of scaling. A vertical architecture, hence, is essential to effectively de-couple gate length scaling and active-area scaling. Vertical nanowire MOSFETs with GAA are the ultimate solution.Another challenge of down-scaling is the increase in power dissipation with transistor density. This calls for a trade-off between operating voltage and switching speed. New channel materials are, thus, necessary to afford voltage reduction without compromising the performance. III-V compound semiconductors are attractive candidates that allow high mobility charge carriers at low operating voltages. Therefore, vertical GAA III-V nanowire devices will be the focus of this study.The PhD work is aimed at achieving the following- Process integration of vertical III-V nanowire devices with top-down approach- Study the effect of EOT scaling, nanowire dimension scaling and channel surface pre-treatments on device performance- Address the contact resistance problem in these nanoscale devices by developing a suitable nanowire resistor test vehicle- Electrical characterization and parameter extraction of the nanowire resistors